1. Field of the Invention
The present invention relates to a semiconductor memory and a control method thereof, and is applicable for example to a flash memory.
2. Description of the Background Art
A semiconductor memory includes for example a main bit line, a sub bit line, memory cells and an amplifier for differential amplification. The sub bit line is connected in parallel to a plurality of memory cells. The sub bit line is connected for example through a transistor to the main bit line. The amplifier has two terminals each connected to the main bit line. One terminal is applicable to the reference side, and the other is applicable to the select side.
Techniques relevant to the present invention are introduced for example in Japanese Patent Application Laid-Open Nos. 4-159694 (1992) and 11-191298 (1999).
As an example, each memory cell may be an MOS transistor having a floating gate between a gate electrode and a gate insulating film. In this MOS transistor, data write and erase operations are realized respectively by injection and discharge of electrons or holes into and from the floating gate. Alternatively, the memory cell may be an MOS transistor in which data write operation is realized by trapping injected electrons or holes in an insulating film.
Like usual data read operation, checkup of write/erase operations, namely, write/erase verify operations follow the process given next. Here, it is assumed one of a plurality of memory cells connected through a sub bit line to a main bit line on the select side is a target for write/erase verify operations. First, this target memory cell is selected. Here, “selection” means, when memory cells are MOS transistors, this target memory cell is turned on while the other memory cells are turned off.
Next, a sub bit line connected to a main bit line on the reference side is selected in correspondence with the sub bit line having connection to the target memory cell. The selected sub bit line on the reference side is subjected to the flow of a comparison current, while all the memory cells connected thereto are turned off. The amplifier compares currents flowing through its terminals on the select side and reference side to thereby check up on write/erase operations.
More specifically, in erase verify operation, a prescribed voltage is applied to the gate electrode of a memory cell as a target for verify operation. If a current flowing through the terminal on the select side is larger than the comparison current, erase operation is verified.
In write verify operation, a prescribed voltage is applied to the gate electrode of a memory cell as a target for verify operation. If a current flowing through the terminal on the select side is smaller than the comparison current, write operation is verified.
When an over-erased memory cell is present for example on the reference side, a leakage current flows from this over-erased memory cell even when it is turned off. This is because, when a memory cell is an n-channel MOS transistor, for example, the threshold voltage thereof decreases as the degree of erasure of the memory cell increases. Then in the over-erased memory cell, the threshold voltage is made smaller than a prescribed value, whereby a current flowing through the terminal of the amplifier on the reference side is made larger than a certain current to flow therethrough.
Thus, in erase verify operation, erase operation of a target memory cell on the select side is not verified until the target memory cell is over-erased. In write verify operation, write operation of a target memory cell on the select side is verified even though write operation to the target memory cell has not reached a sufficient level.
When the over-erased memory cell on the reference side is thereafter subjected to write operation, a total current through the sub bit line on the reference is defined only by the comparison current. This reduces the difference in current between the select and reference sides, causing access delay.
If a memory cell to be subjected to read operation and an over-erased memory cell are connected to the same sub bit line, a leakage current flows from the over-erased memory cell in usual read operation of written data. This causes increase of a current flowing through the terminal of the amplifier on the select side by the leakage current to reduce the difference in current between the terminals on the select and reference sides, thus causing access delay.
If an over-erased memory cell is present on the select side, a leakage current flows from this memory cell in erase verify operation. Thus, erase operation of a memory cell as a target for erase verify operation is verified, even when a current flowing in the target memory cell is smaller than the comparison current by this leakage current, namely, even when erasure fails to reach a desired level. As a result, a memory cell having a threshold voltage larger than a voltage applied in erase verify operation (memory cell failing to reach a sufficient level of erasure) is generated.
When the over-erased memory cell on the select side is thereafter subjected to write operation, a total current through the sub bit line is reduced. When the memory cell failing to reach a sufficient level of erasure is selected in read operation of an erased memory cell, a total current flowing through the sub bit line by the application of a voltage in normal read operation is reduced accordingly, thereby causing access delay.